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TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
Rev. 02 -- 2 February 2007 Product data sheet
1. General description
The TDA6650ATT; TDA6651ATT is a programmable 3-band mixer/oscillator and low phase noise PLL synthesizer intended for pure 3-band tuner concepts applied to hybrid (digital and analog) or digital-only terrestrial and cable TV reception.
Table 1. Different versions are available, depending on the target application[1] Type version TDA6650ATT/C3 TDA6651ATT/C3 Digital only (ISDB-T) TDA6650ATT/C3/S2 TDA6651ATT/C3/S2 TDA6651ATT/C3/S3
[1] See Table 20 "Characteristics" for differences between TDA6651ATT/C3/S2 and TDA6651ATT/C3/S3.
Application Analog and digital (Hybrid ISDB-T/NTSC Japan)
The device includes three double balanced mixers for low, mid and high bands, three oscillators for the corresponding bands, a switchable IF amplifier, a wideband AGC detector and a low noise PLL synthesizer. The frequencies of the three bands are shown in Table 2. Two pins are available between the mixer output and the IF amplifier input to enable IF filtering for improved signal handling and to improve the adjacent channel rejection.
Table 2. Band Recommended band limits RF input Min (MHz) Low Mid High Low Mid High
[1] [2]
Oscillator Max (MHz) 217.25 463.25 765.25 219.00 465.00 767.00 Min (MHz) 150 276 522 150 276 522 Max (MHz) 276 522 824 276 522 824
ISDB-T and NTSC Japan hybrid tuners[1] 91.25 217.25 463.25 93.00 219.00 465.00
ISDB-T tuners for digital-only application[2]
RF input frequency is the frequency of the corresponding picture carrier for analog standard. For bandwidth optimization please refer to Application note AN01014.
The IF amplifier is switchable in order to drive both symmetrical and asymmetrical outputs. When it is used as an asymmetrical amplifier, the IFOUTB pin needs to be connected to the supply voltage VCCA.
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Five open-drain PMOS ports are included on the IC. Two of them, BS1 and BS2, are also dedicated to the selection of the low, mid and high bands. PMOS port BS5 pin is shared with the ADC. The AGC detector provides a control that can be used in a tuner to set the gain of the RF stage. Six AGC take-over points are available by software. Two programmable AGC time constants are available for search tuning and normal tuner operation. The local oscillator signal is fed to the fractional-N divider. The divided frequency is compared to the comparison frequency into the fast phase detector which drives the charge pump. The loop amplifier is also on-chip, including the high-voltage transistor to drive directly the 33 V tuning voltage without the need to add an external transistor. The comparison frequency is obtained from an on-chip crystal oscillator. The crystal frequency can be output to the XTOUT pin to drive the clock input of a digital demodulation IC. Control data is entered via the I2C-bus; six serial bytes are required to address the device, select the Local Oscillator (LO) frequency, select the step frequency, program the output ports and set the charge pump current or enable or disable the crystal output buffer, select the AGC take-over point and time constant and/or select a specific test mode. A status byte concerning the AGC level detector and the ADC voltage can be read out on the SDA line during a read operation. During a read operation, the loop `in-lock' flag, the power-on reset flag and the automatic loop bandwidth control flag are read. The device has 4 programmable addresses. Each address can be selected by applying a specific voltage to pin AS, enabling the use of multiple devices in the same system. The I2C-bus is fast mode compatible, except for the timing as described in the functional description and is compatible with 5 V, 3.3 V and 2.5 V microcontrollers depending on the voltage applied to pin BVS.
2. Features
I Single-chip 5 V mixer/oscillator and low phase noise PLL synthesizer for TV and VCR tuners, dedicated to hybrid (digital and analog) and pure digital applications for Japanese standards (NTSC and ISDB-T) I Five possible step frequencies to cope with different digital terrestrial TV and analog TV standards I Eight charge pump currents between 40 A and 600 A to reach the optimum phase noise performance over the bands I I2C-bus protocol compatible with 2.5 V, 3.3 V and 5 V microcontrollers: N Address + 5 data bytes transmission (I2C-bus write mode) N Address + 1 status byte (I2C-bus read mode) N Four independent I2C-bus addresses I Five PMOS open-drain ports with 15 mA source capability for band switching and general purpose; one of these ports is combined with a 5-step ADC I Wideband AGC detector for internal tuner AGC: N Six programmable take-over points N Two programmable time constants N AGC flag
TDA6650ATT_6651ATT_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
2 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
I I I I I I I I I I
In-lock flag Crystal frequency output buffer 33 V tuning voltage output Fractional-N programmable divider Balanced mixers with a common emitter input for the low band and for the mid band (each single input) Balanced mixer with a common base input for the high band (balanced input) 2-pin asymmetrical oscillator for the low band 2-pin symmetrical oscillator for the mid band 4-pin symmetrical oscillator for the high band Switched concept IF amplifier with both asymmetrical and symmetrical outputs to drive low impedance or SAW filters i.e. 500 /40 pF
3. Applications
For all applications, the recommendations given in the latest Application note AN10544 must be used.
3.1 Application summary
I I I I Digital and analog terrestrial tuners (ISDB-T and NTSC Japan) Cable tuners (QAM) Digital TV sets Digital set-top boxes
4. Ordering information
Table 3. Ordering information Package Name TDA6650ATT/C3 TDA6650ATT/C3/S2 TDA6651ATT/C3 TDA6651ATT/C3/S2 TDA6651ATT/C3/S3 TSSOP38 Description plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0.5 mm Version SOT510-1 Type number
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
3 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
5. Block diagram
IFFIL1 n.c. 21 (18) VCCA 26 (13) 6 (33) IFFIL2 7 (32) 28 (11) IF AMP IFOUTA IFOUTB 27 (12) (30) 9 AGC
TDA6650ATT (TDA6651ATT)
AGC DETECTOR AGC flag AL0, AL1, AL2 ATC (10) 29 (1) 38
IFGND LOSCIN LOSCOUT
LBIN
4 (35)
LOW INPUT
BS1
LOW MIXER
BS1
LOW OSCILLATOR
(2) 37
(5) 34 MBIN 3 (36) MID INPUT BS2 MID MIXER BS2 MID OSCILLATOR (4) 35
MOSCIN1 MOSCIN2
HBIN1 HBIN2
1 (38) 2 (37) HIGH INPUT BS1 . BS2 HIGH MIXER BS1 . BS2 HIGH OSCILLATOR
(9) 30 (8) 31 (7) 32 (6) 33
HOSCIN1 HOSCOUT1 HOSCOUT2 HOSCIN2 OSCGND
RFGND
5 (34)
(3) 36
VCCD
24 (15)
N [14:0]
R0, R1, R2
OUTPUT BUFFER
(21) 18
XTOUT
FRACTIONAL DIVIDER
FRACTIONAL CALCULATOR
PHASE COMPARATOR
T0, T1, T2
LOOP AMP
(17) 22
VT
XTAL1 XTAL2 SCL SDA AS BVS
19 (20) 20 (19) 15 (24) 16 (23) 17 (22) 13 (26) I2C-BUS TRANSCEIVER AGC LOCK DETECTOR CRYSTAL OSCILLATOR REFERENCE DIVIDER CHARGE PUMP (16) 23 CP
T0, T1, CP0, CP1, T2 CP2 FRACTIONAL SPURIOUS COMPENSATION (14) 25 PLLGND
BAND SWITCH OUTPUT PORTS 14 (25) ADC/ BS5 BS4 8 (31) 10 (29) 11 (28) 12 (27)
BS5BS1
POR
ADC
coa033
BS3 BS2
BS1
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 1. Block diagram
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
4 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
6. Pinning information
6.1 Pin description
Table 4. Symbol HBIN1 HBIN2 MBIN LBIN RFGND IFFIL1 IFFIL2 BS4 AGC BS3 BS2 BS1 BVS ADC/BS5 SCL SDA AS XTOUT XTAL1 XTAL2 n.c. VT CP VCCD PLLGND VCCA IFOUTB IFOUTA IFGND HOSCIN1 HOSCOUT1 HOSCOUT2
TDA6650ATT_6651ATT_2
Pin description Pin TDA6650ATT TDA6651ATT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 high band RF input 1 high band RF input 2 mid band RF input low band RF input RF ground IF filter output 1 IF filter output 2 PMOS open-drain output port 4 for general purpose AGC output PMOS open-drain output port 3 for general purpose PMOS open-drain output port 2 to select the mid band PMOS open-drain output port 1 to select the low band bus voltage selection input ADC input or PMOS open-drain output port 5 for general purpose I2C-bus serial clock input I2C-bus serial data input and output I2C-bus address selection input crystal frequency buffer output crystal oscillator input 1 crystal oscillator input 2 not connected tuning voltage output charge pump output supply voltage for the PLL part PLL ground supply voltage for the analog part IF output B for symmetrical amplifier and asymmetrical IF amplifier switch input IF output A IF ground high band oscillator input 1 high band oscillator output 1 high band oscillator output 2
(c) NXP B.V. 2007. All rights reserved.
Description
Product data sheet
Rev. 02 -- 2 February 2007
5 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Pin description ...continued Pin TDA6650ATT TDA6651ATT 33 34 35 36 37 38 6 5 4 3 2 1 Description high band oscillator input 2 mid band oscillator input 1 mid band oscillator input 2 oscillators ground low band oscillator output low band oscillator input
Table 4. Symbol HOSCIN2 MOSCIN1 MOSCIN2 OSCGND LOSCOUT LOSCIN
6.2 Pinning
HBIN1 HBIN2 MBIN LBIN RFGND IFFIL1 IFFIL2 BS4 AGC
1 2 3 4 5 6 7 8 9
38 LOSCIN 37 LOSCOUT 36 OSCGND 35 MOSCIN2 34 MOSCIN1 33 HOSCIN2 32 HOSCOUT2 31 HOSCOUT1 30 HOSCIN1
LOSCIN LOSCOUT OSCGND MOSCIN2 MOSCIN1 HOSCIN2 HOSCOUT2 HOSCOUT1 HOSCIN1
1 2 3 4 5 6 7 8 9
38 HBIN1 37 HBIN2 36 MBIN 35 LBIN 34 RFGND 33 IFFIL1 32 IFFIL2 31 BS4 30 AGC
BS3 10 BS2 11 BS1 12 BVS 13 ADC/BS5 14 SCL 15 SDA 16 AS 17 XTOUT 18 XTAL1 19
TDA6650ATT
29 IFGND 28 IFOUTA 27 IFOUTB 26 VCCA 25 PLLGND 24 VCCD 23 CP 22 VT 21 n.c. 20 XTAL2
IFGND 10 IFOUTA 11 IFOUTB 12 VCCA 13 PLLGND 14 VCCD 15 CP 16 VT 17 n.c. 18 XTAL2 19
TDA6651ATT
29 BS3 28 BS2 27 BS1 26 BVS 25 ADC/BS5 24 SCL 23 SDA 22 AS 21 XTOUT 20 XTAL1
001aac086
001aac087
Fig 2. Pin configuration TDA6650ATT
Fig 3. Pin configuration TDA6651ATT
7. Functional description
7.1 Mixer, Oscillator and PLL (MOPLL) functions
Bit BS1 enables the BS1 port, the low band mixer and the low band oscillator. Bit BS2 enables the BS2 port, the mid band mixer and the mid band oscillator. When both BS1 and BS2 bits are logic 0, the high band mixer and the high band oscillator are enabled. The oscillator signal is applied to the fractional-N programmable divider. The divided signal fdiv is fed to the phase comparator where it is compared in both phase and frequency with the comparison frequency fcomp. This frequency is derived from the signal present on the crystal oscillator fxtal and divided in the reference divider. There is a fractional calculator on the chip that generates the data for the fractional divider as well as
TDA6650ATT_6651ATT_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
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NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
the reference divider ratio, depending on the step frequency selected. The crystal oscillator requires a 4 MHz crystal in series with an 18 pF capacitor between pins XTAL1 and XTAL2. The output of the phase comparator drives the charge pump and the loop amplifier section. This amplifier has an on-chip high voltage drive transistor. Pin CP is the output of the charge pump, and pin VT is the pin to drive the tuning voltage to the varicap diodes of the oscillators and the tracking filters. The loop filter has to be connected between pins CP and VT. The spurious signals introduced by the fractional divider are automatically compensated by the spurious compensation block. It is possible to drive the clock input of a digital demodulation IC from pin XTOUT with the 4 MHz signal from the crystal oscillator. This output is also used to output 12fdiv and fcomp signals in a specific test mode (see Table 9). It is possible to switch off this output, which is recommended when it is not used. For test and alignment purposes, it is also possible to release the tuning voltage output by selecting the sinking mode (see Table 9), and by applying an external voltage on pin VT. In addition to the BS1 and BS2 output ports that are used for the band selection, there are three general purpose ports BS3, BS4 and BS5. All five ports are PMOS open-drain type, each with 15 mA drive capability. The connection for port BS5 and the ADC input is combined on one pin. It is not possible to use the ADC if port BS5 is used. The AGC detector compares the level at the IF amplifier output to a reference level which is selected from 6 different levels via the I2C-bus. The time constant of the AGC can be selected via the I2C-bus to cope with normal operation as well as with search operation. When the output level on pin AGC is higher than the threshold VRMH, then bit AGC = 1. When the output level on pin AGC is lower than the threshold VRML, then bit AGC = 0. Between these two thresholds, bit AGC is not defined. The status of the AGC bit can be read via the I2C-bus according to the read mode as described in Table 13.
7.2 I2C-bus voltage
The I2C-bus lines SCL and SDA can be connected to an I2C-bus system tied to 2.5 V, 3.3 V or 5 V. The choice of the bus input threshold voltages is made with pin BVS that can be left open-circuit, connected to the supply voltage or to ground (see Table 5).
Table 5. I2C-bus voltage selection Bus voltage 2.5 V 3.3 V 5V Logic level LOW To ground Open-circuit To VCC 0 V to 0.75 V 0 V to 1.0 V 0 V to 1.5 V HIGH 1.75 V to 5.5 V 2.3 V to 5.5 V 3.0 V to 5.5 V
Pin BVS connection
7.3 Phase noise, I2C-bus traffic and crosstalk
While the TDA6650ATT; TDA6651ATT is dedicated for hybrid terrestrial applications, the low noise PLL will clean up the noise spectrum of the VCOs close to the carrier to reach noise levels at 1 kHz offset from the carrier compatible with e.g. ISDB-T reception.
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
7 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Linked to this noise improvement, some disturbances may become visible while they were not visible because they were hidden into the noise in analog dedicated applications and circuits. This is especially true for disturbances coming from the I2C-bus traffic, whatever this traffic is intended for the MOPLL or for another slave on the bus. To avoid this I2C-bus crosstalk and be able to have a clean noise spectrum, it is necessary to use a bus gate that enables the signal on the bus to drive the MOPLL only when the communication is intended for the tuner part (such a kind of I2C-bus gate is included into the NXP terrestrial channel decoders), and to avoid unnecessary repeated sending of the same information.
8. I2C-bus protocol
The TDA6650ATT; TDA6651ATT is controlled via the two-wire I2C-bus. For programming, there is one device address (7 bits) and the R/W bit for selecting read or write mode. To be able to have more than one MOPLL in an I2C-bus system, one of four possible addresses is selected depending on the voltage applied to address selection pin AS (see Table 8). The TDA6650ATT; TDA6651ATT fulfils the fast mode I2C-bus, according to the NXP I2C-bus specification, except for the timing as described in Figure 4. The I2C-bus interface is designed in such a way that the pins SCL and SDA can be connected to 5 V, 3.3 V or to 2.5 V pulled-up I2C-bus lines, depending on the voltage applied to pin BVS (see Table 5).
8.1 Write mode; R/W = 0
After the address transmission (first byte), data bytes can be sent to the device (see Table 6). Five data bytes are needed to fully program the TDA6650ATT; TDA6651ATT. The I2C-bus transceiver has an auto-increment facility that permits programming the device within one single transmission (address + 5 data bytes). The TDA6650ATT; TDA6651ATT can also be partly programmed on the condition that the first data byte following the address is byte 2 (divider byte 1) or byte 4 (control byte 1). The first bit of the first data byte transmitted indicates whether byte 2 (first bit = 0) or byte 4 (first bit = 1) will follow. Until an I2C-bus STOP condition is sent by the controller, additional data bytes can be entered without the need to re-address the device. The fractional calculator is updated only at the end of the transmission (STOP condition). Each control byte is loaded after the 8th clock pulse of the corresponding control byte. Main divider data are valid only if no new I2C-bus transmission is started (START condition) during the computation period of 50 s. Both DB1 and DB2 need to be sent to change the main divider ratio. If the value of the ratio selection bits R2, R1 and R0 are changed, the bytes DB1 and DB2 have to be sent in the same transmission.
TDA6650ATT_6651ATT_2
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Product data sheet
Rev. 02 -- 2 February 2007
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NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
50 s START ADDRESS DIVIDER BYTE BYTE 1 DIVIDER CONTROL CONTROL CONTROL CONTROL STOP BYTE 2 BYTE 1 BYTE 2 BYTE 1 BYTE 2 I2C-bus transmission dedicated to the MOPLL START ADDRESS BYTE
I2C-bus transmission dedicated to another IC
fce921
Fig 4. Example of I2C-bus transmission frame Table 6. Name Address byte Divider byte 1 (DB1) Divider byte 2 (DB2) Control byte 1 (CB1); see Table 7 Control byte 2 (CB2)
[1]
I2C-bus write data format Byte 1 2 3 4 5 Bit MSB[1] 1 0 N7 1 1 CP2 1 N14 N6 T/A = 1 T/A = 0 CP1 0 N13 N5 T2 0 CP0 0 N12 N4 T1 0 BS5 0 N11 N3 T0 ATC BS4 MA1 N10 N2 R2 AL2 BS3 MA0 N9 N1 R1 AL1 BS2 LSB R/W = 0 A N8 N0 R0 AL0 BS1 A A A A A Ack
MSB is transmitted first.
Table 7. Bit A
Description of write data format bits Description acknowledge programmable address bits; see Table 8 logic 0 for write mode programmable LO frequency; N = N14 x 214 + N13 x 213 + N12 x 212 + ... + N1 x 21 + N0 test/AGC bit T/A = 0: the next 6 bits sent are AGC settings T/A = 1: the next 6 bits sent are test and reference divider ratio settings
MA1 and MA0 R/W N14 to N0 T/A
T2, T1 and T0 R2, R1, and R0 ATC
test bits; see Table 9 reference divider ratio and programmable frequency step; see Table 10 AGC current setting and time constant; capacitor on pin AGC = 150 nF ATC = 0: AGC current = 220 nA; AGC time constant = 2 s ATC = 1: AGC current = 9 A; AGC time constant = 50 ms
AL2, AL1 and AL0 CP2, CP1 and CP0
AGC take-over point bits; see Table 11 charge pump current; see Table 12
BS5, BS4, BS3, BS2 PMOS ports control bits and BS1 BSn = 0: corresponding port is off, high-impedance state (status at power-on reset) BSn = 1: corresponding port is on; VO = VCC - VDS(sat)
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
9 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
8.1.1 I2C-bus address selection
The device address contains programmable address bits MA1 and MA0, which offer the possibility of having up to four MOPLL ICs in one system. Table 8 gives the relationship between the voltage applied to the AS input and the MA1 and MA0 bits.
Table 8. Address selection MA1 0 0 1 1 MA0 0 1 0 1
Voltage applied to pin AS 0 V to 0.1VCC 0.2VCC to 0.3VCC or open-circuit 0.4VCC to 0.6VCC 0.9VCC to VCC
8.1.2 XTOUT output buffer and mode setting
The crystal frequency can be sent to pin XTOUT and used in the application, for example to drive the clock input of a digital demodulator, saving a quartz crystal in the bill of material. To output fxtal, it is necessary to set T[2:0] to 001. If the output signal on this pin is not used, it is recommended to disable it, by setting T[2:0] to 000. This pin is also used to output 12fdiv and fcomp in a test mode. At power-on, the XTOUT output buffer is set to on, supplying the fxtal signal. The relation between the signal on pin XTOUT and the setting of the T[2:0] bits is given in Table 9.
Table 9. T2 0 0 0 0 1 1 1 1
[1] [2]
XTOUT buffer status and test modes T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 Pin XTOUT disabled fxtal (4 MHz)
1 f 2 div
Mode normal mode with XTOUT buffer off normal mode with XTOUT buffer on charge pump off not used[1] test mode test mode charge pump sinking current[2] charge pump sourcing current
fxtal (4 MHz) fcomp
1 f 2 div
fxtal (4 MHz) disabled
This is an on-chip function that automatically sets internal values for the PLL. This function is not optimized for ISDB-T and NTSC Japan and therefore must not be used. This is the default mode at power-on reset. This mode disables the tuning voltage.
8.1.3 Step frequency setting
The step frequency is set by three bits, giving five steps to cope with different application requirements. The reference divider ratio is automatically set depending on bits R2, R1 and R0. The phase detector works at either 4 MHz, 2 MHz or 1 MHz. Table 10 shows the step frequencies and corresponding reference divider ratios. When the value of bits R2, R1 and R0 are changed, it is necessary to re-send the data bytes DB1 and DB2.
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
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NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Reference divider ratio select bits R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 Reference divider Frequency ratio comparison 2 1 1 4 1 2 MHz 4 MHz 4 MHz 1 MHz 4 MHz Frequency step 62.5 kHz 142.86 kHz 166.67 kHz 50 kHz 125 kHz reserved reserved reserved
Table 10. R2 0 0 0 0 1 1 1 1
8.1.4 AGC detector setting
The AGC take-over point can be selected out of 6 levels according to Table 11.
Table 11. AL2 0 0 0 0 1 1 1 1
[1] [2] [3] [4]
AGC programming AL1 0 0 1 1 0 0 1 1 AL0 0 1 0 1 0 1 0 1
[1] [1] [1] [2] [2] [2] [3] [4]
Typical take-over point level 124 dBV (p-p) 121 dBV (p-p) 118 dBV (p-p) 115 dBV (p-p) 112 dBV (p-p) 109 dBV (p-p) IAGC = 0 A VAGC = 3.5 V
This take-over point is available for both symmetrical and asymmetrical modes. This take-over point is available for asymmetrical mode only. The AGC current sources are disabled. The AGC output goes into a high-impedance state and an external AGC source can be connected in parallel and will not be influenced. The AGC detector is disabled and IAGC = 9 A.
8.1.5 Charge pump current setting
The charge pump current can be chosen from 8 values depending on the value of bits CP2, CP1 and CP0 bits; see Table 12.
Table 12. CP2 0 0 0 0 1 Charge pump current CP1 0 0 1 1 0 CP0 0 1 0 1 0 Charge pump current number 1 2 3 4 5 Typical current (absolute value in A) 38 54 83 122 163
TDA6650ATT_6651ATT_2
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Product data sheet
Rev. 02 -- 2 February 2007
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NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Charge pump current ...continued CP1 0 1 1 CP0 1 0 1 Charge pump current number 6 7 8 Typical current (absolute value in A) 254 400 580
Table 12. CP2 1 1 1
8.2 Read mode; R/W = 1
Data can be read from the device by setting the R/W bit to 1 (see Table 13). After the device address has been recognized, the device generates an acknowledge pulse and the first data byte (status byte) is transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL clock signal. A second data byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge). End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the microcontroller to generate a STOP condition.
Table 13. Name I2C-bus read data format Byte Bit MSB[1] Address byte 1 Status byte
[1]
Ack LSB 1 FL 0 0 0 1 0 AGC MA1 A2 MA0 A1 R/W = 1 A A0 -
1 POR
2
MSB is transmitted first.
Table 14. Bit A POR
Description of read data format bits Description acknowledge power-on reset flag POR = 0, normal operation POR = 1, power-on reset
FL
in-lock flag FL = 0, not locked FL = 1, the PLL is locked
AGC
internal AGC flag AGC = 0 when internal AGC is active (VAGC < VRML) AGC = 1 when internal AGC is not active (VAGC > VRMH)
A2, A1, A0 Table 15.
digital outputs of the 5-level ADC; see Table 15 ADC levels A2 1 0 A1 0 1 A0 0 1
Voltage applied to pin ADC[1] 0.6VCC to VCC 0.45VCC to 0.6VCC
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
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NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
ADC levels ...continued A2 0 0 0 A1 1 0 0 A0 0 1 0
Table 15.
Voltage applied to pin ADC[1] 0.3VCC to 0.45VCC 0.15VCC to 0.3VCC 0 V to 0.15VCC
[1]
Accuracy is 0.03VCC. Bit BS5 must be set to logic 0 to disable the BS5 output port. The BS5 output port uses the same pin as the ADC and can not be used when the ADC is in use.
8.3 Status at power-on reset
At power on or when the supply voltage drops below approximately 2.85 V (at Tamb = 25 C), internal registers are set according to Table 16. At power on, the charge pump current is set to 580 A, the test bits T[2:0] are set to 110 which means that the charge pump is sinking current, the tuning voltage output is disabled. The XTOUT buffer is on, driving the 4 MHz signal from the crystal oscillator and all the ports are off. As a consequence, the high band is selected by default.
Table 16. Name Address byte Divider byte 1 (DB1) Divider byte 2 (DB2) Control byte 1 (CB1) Control byte 2 (CB2)
[1] [2] [3]
Default setting at power-on reset Byte 1 2 3 4 5 Bit[1] MSB 1 0 N7 = X 1 1 CP2 = 1 1 N14 = X N6 = X T/A = X[2] T/A = X[3] CP1 = 1 0 N13 = X N5 = X T2 = 1 0 CP0 = 1 0 N12 = X N4 = X T1 = 1 0 BS5 = 0 0 N11 = X N3 = X T0 = 0 ATC = 0 BS4 = 0 MA1 N10 = X N2 = X R2 = X AL2 = 0 BS3 = 0 MA0 N9 = X N1 = X R1 = X AL1 = 1 BS2 = 0 LSB X N8 = X N0 = X R0 = X AL0 = 0 BS1 = 0
X means that this bit is not set or reset at power-on reset. The next six bits are written, when bit T/A = 1 in a write sequence. The next six bits are written, when bit T/A = 0 in a write sequence.
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
13 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
9. Internal circuitry
Table 17. Symbol Internal pin configuration Pin TDA6650ATT HBIN1 HBIN2 1 2 TDA6651ATT 38 37 Average DC voltage versus band selection Low n.a. n.a. Mid n.a. n.a. High 1.0 V 1.0 V
(38) 1 2 (37)
Description[1]
fce899
MBIN
3
36
n.a.
1.8 V
n.a.
(36) 3
fce901
LBIN
4
35
1.8 V
n.a.
n.a.
(35) 4
fce898
RFGND
5
34
-
-
5 (34)
fce897
IFFIL1 IFFIL2
6 7
33 32
3.7 V 3.7 V
3.7 V 3.7 V
3.7 V 3.7 V
(33) 6 7 (32)
fce896
BS4
8
31
high-Z or high-Z or high-Z or VCC - VDS VCC - VDS VCC - VDS
8 (31)
fce895
TDA6650ATT_6651ATT_2
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Product data sheet
Rev. 02 -- 2 February 2007
14 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 17. Symbol
Internal pin configuration ...continued Pin TDA6650ATT TDA6651ATT 30 Average DC voltage versus band selection Low 0 V or 3.5 V Mid 0 V or 3.5 V High 0 V or 3.5 V
9 (30)
Description[1]
AGC
9
fce907
BS3
10
29
high-Z or high-Z or high-Z or VCC - VDS VCC - VDS VCC - VDS
10 (29)
fce893
BS2
11
28
high-Z
VCC - VDS high-Z
11 (28)
fce892
BS1
12
27
VCC - VDS high-Z
high-Z
12 (27)
fce891
BVS
13
26
2.5 V
2.5 V
2.5 V
(26) 13
mce163
ADC/BS5
14
25
VCEsat or high-Z
VCEsat or high-Z
VCEsat or high-Z
(25) 14
fce887
TDA6650ATT_6651ATT_2
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Product data sheet
Rev. 02 -- 2 February 2007
15 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 17. Symbol
Internal pin configuration ...continued Pin TDA6650ATT TDA6651ATT 24 Average DC voltage versus band selection Low high-Z Mid high-Z High high-Z Description[1]
SCL
15
(24) 15
fce889
SDA
16
23
high-Z
high-Z
high-Z
(23) 16
fce888
AS
17
22
1.25 V
1.25 V
1.25 V
(22) 17
001aac102
XTOUT
18
21
3.45 V
3.45 V
3.45 V
18 (21)
mce164
XTAL1 XTAL2
19 20
20 19
2.2 V 2.2 V
2.2 V 2.2 V
2.2 V 2.2 V
19 (20)
20 (19)
fce883
n.c.
21
18
n.a.
n.a.
n.a.
not connected
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
16 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 17. Symbol
Internal pin configuration ...continued Pin TDA6650ATT TDA6651ATT 17 Average DC voltage versus band selection Low VVT Mid VVT High VVT
22 (17)
Description[1]
VT
22
fce884
CP
23
16
1.8 V
1.8 V
1.8 V
23 (16)
fce885
VCCD PLLGND
24 25
15 14
5V -
5V -
5V 25 (14)
fce882
VCCA IFOUTB IFOUTA
26 27 28
13 12 11
5V 2.1 V 2.1 V
5V 2.1 V 2.1 V
5V 2.1 V 2.1 V
28 (11)
fce886
IFGND
29
10
-
-
29 (10)
fce880
HOSCIN1 HOSCOUT1 HOSCOUT2 HOSCIN2
30 31 32 33
9 8 7 6
2.2 V 5V 5V 2.2 V
2.2 V 5V 5V 2.2 V
1.8 V 2.5 V 2.5 V 1.8 V
(8) 31 (6) 33 32 (7) 30 (9)
fce879
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
17 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 17. Symbol
Internal pin configuration ...continued Pin TDA6650ATT TDA6651ATT 5 4 Average DC voltage versus band selection Low 2.3 V 2.3 V Mid 1.3 V 1.3 V High 2.3 V 2.3 V Description[1]
MOSCIN1 MOSCIN2
34 35
34 (5)
35 (4)
fce878
OSCGND
36
3
-
-
36 (3)
fce908
LOSCOUT LOSCIN
37 38
2 1
1.7 V 2.9 V
1.4 V 3.5 V
1.4 V 3.5 V
37 (2) (1) 38
fce877
[1]
The pin numbers in parenthesis refer to the TDA6651ATT.
10. Limiting values
Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Positive currents are entering the IC and negative currents are going out of the IC; all voltages are referenced to ground (GND)[1]. Symbol VCCA VCCD VVT VSDA ISDA VSCL VAS Parameter analog supply voltage digital supply voltage tuning voltage output serial data input and output voltage serial data output current serial clock input voltage address selection input voltage during acknowledge Conditions Min -0.3 -0.3 -0.3 -0.3 0 -0.3 -0.3 Max +6 +6 +35 +6 10 +6 +6 Unit V V V V mA V V
TDA6650ATT_6651ATT_2
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Product data sheet
Rev. 02 -- 2 February 2007
18 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 18. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Positive currents are entering the IC and negative currents are going out of the IC; all voltages are referenced to ground (GND)[1]. Symbol Vn Parameter voltage on all other inputs, outputs and combined inputs and outputs, except GNDs PMOS port output current Conditions 4.5 V < VCC < 5.5 V
[2]
Min -0.3
Max VCC + 0.3
Unit V
IBSn IBS(tot) tsc(max) Tstg Tamb Tj
[1] [2] [3]
corresponding port on; open-drain
-20 -50 -40
[3]
0 0 10 +150 Tamb(max) 150
mA mA s C C C
sum of all PMOS port output open-drain currents maximum short-circuit time storage temperature ambient temperature junction temperature each pin to VCC or to GND
-20 -
Maximum ratings cannot be exceeded, not even momentarily without causing irreversible IC damage. Maximum ratings cannot be accumulated. VCC refers to the operating supply voltage. The maximum allowed ambient temperature Tamb(max) depends on the assembly conditions of the package and especially on the design of the printed-circuit board. The application mounting must be done in such a way that the maximum junction temperature is never exceeded. An estimation of the junction temperature can be obtained through measurement of the temperature of the top center of the package (Tpackage). The temperature difference junction to case (Tj-c) is estimated at about 13 C on the demo board (PCB 827-3). The junction temperature Tj = Tpackage + Tj-c.
11. Thermal characteristics
Table 19. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient TDA6650ATT TDA6651ATT
[1] [2] Measured in free air as defined by JEDEC standard JESD51-2. These values are given for information only. The thermal resistance depends strongly on the nature and design of the printed-circuit board used in the application. The thermal resistance given corresponds to the value that can be measured on a multilayer printed-circuit board (4 layers) as defined by JEDEC standard. The junction temperature influences strongly the reliability of an IC. The printed-circuit board used in the application contributes in a large part to the overall thermal characteristic. It must therefore be insured that the junction temperature of the IC never exceeds T j(max) = 150 C at the maximum ambient temperature.
Conditions in free air
[1][2][3]
Typ
Unit
82 74
K/W K/W
[3]
TDA6650ATT_6651ATT_2
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Product data sheet
Rev. 02 -- 2 February 2007
19 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
12. Characteristics
Table 20. Characteristics VCCA = VCCD = 5 V; Tamb = 25 C; values are given for an asymmetrical IF output loaded with a 75 load or with a symmetrical IF output loaded with 1.25 k; positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified. Symbol Supply VCC ICC supply voltage supply current PMOS ports off one PMOS port on: sourcing 15 mA two PMOS ports on: one port sourcing 15 mA and one other port sourcing 5 mA General functions VPOR flock power-on reset supply voltage frequency range the PLL is able to synthesize crystal frequency input impedance (absolute value) crystal drive level fxtal = 4 MHz; VCC = 4.5 V to 5.5 V Tamb = -20 C to Tamb(max), see Section 10 fxtal = 4 MHz
[2]
Parameter
Conditions
Min 4.5 80 96 101
Typ 5.0 96 112 117
Max 5.5 115 131 136
Unit V mA mA mA
power-on reset active if VCC < VPOR
64
2.85 -
3.5 1024
V MHz
Crystal oscillator[1] fxtal Zxtal 350 4.0 430 MHz
Pxtal ILO(off) VDS(sat)
-10 -
70 0.2
0.4
W A V
PMOS ports: pins BS1, BS2, BS3, BS4 and BS5 output leakage current in VCC = 5.5 V; VBS = 0 V off state output saturation voltage only corresponding buffer is on, sourcing 15 mA; VDS(sat) = VCC - VBS ADC input voltage LOW-level input current see Table 15 VADC = 0 V
ADC input: pin ADC Vi IIH IIL IIH IIL IIH IIL Vo(p-p) 0 -10 -10 -100
[3]
400
5.5 10 10 100 -
V A A A A A A mV
HIGH-level input current VADC = VCC
Address selection input: pin AS HIGH-level input current VAS = 5.5 V LOW-level input current VAS = 0 V
Bus voltage selection input: pin BVS HIGH-level input current VBVS = 5.5 V LOW-level input current square wave AC output voltage (peak-to-peak value) output impedance VBVS = 0 V
Buffered output: pin XTOUT -
Zo
-
175
-
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
20 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics ...continued VCCA = VCCD = 5 V; Tamb = 25 C; values are given for an asymmetrical IF output loaded with a 75 load or with a symmetrical IF output loaded with 1.25 k; positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified. Symbol I2C-bus Inputs: pins SCL and SDA fclk VIL clock frequency LOW-level input voltage frequency on SCL VBVS = 0 V VBVS = 2.5 V or open-circuit VBVS = 5 V VIH HIGH-level input voltage VBVS = 0 V VBVS = 2.5 V or open-circuit VBVS = 5 V IIH IIL HIGH-level input current VCC = 0 V; VBUS = 5.5 V VCC = 5.5 V; VBUS = 5.5 V LOW-level input current VCC = 0 V; VBUS = 1.5 V VCC = 5.5 V; VBUS = 0 V Output: pin SDA ILH VO(ack) leakage current output voltage during acknowledge output current (absolute value) VSDA = 5.5 V ISDA = 3 mA 10 0.4 A V 0 0 0 1.75 2.3 3.0 -10 400 0.75 1.0 1.5 5.5 5.5 5.5 10 10 10 kHz V V V V V V A A A A Parameter Conditions Min Typ Max Unit
Charge pump output: pin CP Io IL(off) IL(off) Vo(cl) see Table 12 -15 0.3 0 +15 10 32.7 A nA A V
off-state leakage current charge pump off (T[2:0] = 010) leakage current when switched-off output voltage when the loop is closed tuning supply voltage = 33 V tuning supply voltage = 33 V; RL = 15 k
Tuning voltage output: pin VT
Noise performance J(rms) phase jitter (RMS value) integrated between 1 kHz and 1 MHz offset from the carrier digital application: TDA6650ATT/C3/S2, TDA6651ATT/C3/S2, TDA6651ATT/C3/S3 hybrid application: TDA6650ATT/C3, TDA6651ATT/C3 0.5 deg
-
0.6
-
deg
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
21 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics ...continued VCCA = VCCD = 5 V; Tamb = 25 C; values are given for an asymmetrical IF output loaded with a 75 load or with a symmetrical IF output loaded with 1.25 k; positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified. Symbol fRF Parameter RF frequency Conditions picture carrier for hybrid application TDA6650ATT/C3, TDA6651ATT/C3 picture carrier for digital-only application TDA6650ATT/C3/S2, TDA6651ATT/C3/S2, TDA6651ATT/C3/S3 Gv voltage gain asymmetrical IF output; RL = 75 ; see Figure 14 fRF = 91.25 MHz fRF = 219.143 MHz symmetrical IF output; RL = 1.25 k; see Figure 15 fRF = 91.25 MHz fRF = 219.143 MHz NF Vo noise figure output voltage causing 1 % cross modulation in channel fRF = 150 MHz asymmetrical application; see Figure 18 fRF = 91.25 MHz fRF = 219.143 MHz symmetrical application; see Figure 19 fRF = 91.25 MHz fRF = 219.143 MHz Vi input voltage causing 750 Hz frequency deviation pulling in channel input level without lock-out input conductance input capacitance asymmetrical IF output
[5] [5] [4]
Min 91.25 93.00
Typ -
Max
Unit
Low band mixer, including IF amplifier 219.143 MHz 220.893 MHz
[4]
20 20
23.5 24.0
26 26
dB dB
25 25 -
27.5 27.5 7
31 31 10
dB dB dB
107 107
110 110
-
dBV dBV
117 117 -
120 120 85
-
dBV dBV dBV
Vi(lock) Gi Ci
see Figure 25 fRF = 91.25 MHz; see Figure 5 fRF = 219.43 MHz; see Figure 5 fRF = 91.25 MHz to 219.43 MHz; see Figure 5 for hybrid application TDA6650ATT/C3, TDA6651ATT/C3 picture carrier for digital only application TDA6650ATT/C3/S2, TDA6651ATT/C3/S2, TDA6651ATT/C3/S3
[7]
-
0.15 0.20 1.60
120 -
dBV mS mS pF
Mid band mixer, including IF amplifier foper operating frequency 163.25 165.00 465.143 MHz 466.893 MHz
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
22 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics ...continued VCCA = VCCD = 5 V; Tamb = 25 C; values are given for an asymmetrical IF output loaded with a 75 load or with a symmetrical IF output loaded with 1.25 k; positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified. Symbol fRF Parameter RF frequency Conditions picture carrier for hybrid application TDA6650ATT/C3, TDA6651ATT/C3 picture carrier for digital only application TDA6650ATT/C3/S2, TDA6651ATT/C3/S2, TDA6651ATT/C3/S3 Gv voltage gain asymmetrical IF output; load = 75 ; see Figure 14 fRF = 223.25 MHz fRF = 465.143 MHz symmetrical IF output; load = 1.25 k; see Figure 15 fRF = 223.25 MHz fRF = 465.143 MHz NF Vo noise figure output voltage causing 1 % cross modulation in channel fRF = 300 MHz; see Figure 17 asymmetrical application; see Figure 18 fRF = 223.25 MHz fRF = 465.143 MHz symmetrical application; see Figure 19 fRF = 223.25 MHz fRF = 465.143 MHz Vi input voltage causing 750 Hz frequency deviation pulling in channel input level without lock-out input conductance input capacitance operating frequency asymmetrical IF output
[5] [5] [4]
Min 223.25 225.00
Typ -
Max
Unit
465.143 MHz 466.893 MHz
[4]
20 20
23.5 24
26 26
dB dB
25 25 -
27 27.5 8
31 31 11
dB dB dB
107 107
110 110
-
dBV dBV
117 117 -
120 120 87
-
dBV dBV dBV
Vi(lock) Gi Ci foper
see Figure 25 see Figure 6 see Figure 6 for hybrid application TDA6650ATT/C3, TDA6651ATT/C3 picture carrier for digital only application TDA6650ATT/C3/S2, TDA6651ATT/C3/S2, TDA6651ATT/C3/S3
[7]
355.25 357.00
0.3 1.1 -
120 -
dBV mS pF
High band mixer, including IF amplifier 767.143 MHz 768.893 MHz
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
23 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics ...continued VCCA = VCCD = 5 V; Tamb = 25 C; values are given for an asymmetrical IF output loaded with a 75 load or with a symmetrical IF output loaded with 1.25 k; positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified. Symbol fRF Parameter RF frequency Conditions picture carrier for hybrid application TDA6650ATT/C3, TDA6651ATT/C3 picture carrier for digital only application TDA6650ATT/C3/S2, TDA6651ATT/C3/S2, TDA6651ATT/C3/S3 Gv voltage gain asymmetrical IF output; load = 75 ; see Figure 20 fRF = 471.25 MHz fRF = 767.143 MHz symmetrical IF output; load = 1.25 k; see Figure 21 fRF = 471.25 MHz fRF = 767.143 MHz NF noise figure, not corrected for image see Figure 22 fRF = 471.25 MHz fRF = 767.143 MHz Vo output voltage causing 1 % cross modulation in channel asymmetrical application; see Figure 23 fRF = 471.25 MHz fRF = 767.143 MHz symmetrical application; see Figure 24 fRF = 471.25 MHz fRF = 767.143 MHz Vi(lock) Vi input level without lock-out input voltage causing 750 Hz frequency deviation pulling in channel input impedance (RS + jLS) see Figure 26 asymmetrical IF output
[7] [5] [5] [4]
Min 471.25 473.00
Typ -
Max
Unit
767.143 MHz 768.893 MHz
[4]
31.5 31.5
35 33.5
37.5 37.5
dB dB
35.5 35.5 -
38.5 37 6 7
41.5 41.5 8 9
dB dB dB dB
107 107
110 110
-
dBV dBV
117 117 -
120 120 75
120 -
dBV dBV dBV dBV
Zi
fRF = 471.25 MHz; see Figure 7 RS LS fRF = 767.143 MHz; see Figure 7 RS LS [7] [8]
-
35 8 36 8 110
-
nH nH
Low band oscillator fosc fosc(V) oscillator frequency oscillator frequency shift with supply voltage 150 276.143 MHz 300 kHz
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
24 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics ...continued VCCA = VCCD = 5 V; Tamb = 25 C; values are given for an asymmetrical IF output loaded with a 75 load or with a symmetrical IF output loaded with 1.25 k; positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified. Symbol fosc(T) osc(dig) Parameter oscillator frequency drift with temperature Conditions T = 25 C; VCC = 5 V with compensation
[9]
Min -
Typ 900
Max -
Unit kHz
phase noise, carrier to TDA6650ATT/C3/S2; sideband noise in digital TDA6651ATT/C3/S2; application TDA6651ATT/C3/S3 1 kHz frequency offset; fcomp = 4 MHz; see Figure 8, 27 and 28 10 kHz frequency offset; worst case in the frequency range; see Figure 9, 27 and 28 100 kHz frequency offset; worst case in the frequency range; see Figure 10, 27 and 28 1.4 MHz frequency offset; worst case in the frequency range; see Figure 27 and 28 82 90 dBc/Hz
87
94
-
dBc/Hz
104
115
-
dBc/Hz
-
117
-
dBc/Hz
osc(hyb)
phase noise, carrier to TDA6650ATT/C3; TDA6651ATT/C3 sideband noise in hybrid 1 kHz frequency offset; application fcomp = 4 MHz; see Figure 11, 29 and 30 10 kHz frequency offset; worst case in the frequency range; see Figure 12, 29 and 30 100 kHz frequency offset; worst case in the frequency range; see Figure 13, 29 and 30 1.4 MHz frequency offset; worst case in the frequency range; see Figure 29 and 30
75
81
-
dBc/Hz
85
92
-
dBc/Hz
104
115
-
dBc/Hz
-
117
-
dBc/Hz
RSCp-p
ripple susceptibility of VCC (peak-to-peak value) oscillator operating frequency oscillator frequency
VCC = 5 V 5 %; worst case in the frequency range; ripple frequency 500 kHz
[10]
15
200
-
mV
Mid band oscillator fosc 222
[7] [8]
300 1500
522.143 MHz 522.143 MHz kHz kHz
276 -
fosc(V) fosc(T)
oscillator frequency shift with supply voltage oscillator frequency drift with temperature T = 25 C; VCC = 5 V with compensation
[9]
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
25 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics ...continued VCCA = VCCD = 5 V; Tamb = 25 C; values are given for an asymmetrical IF output loaded with a 75 load or with a symmetrical IF output loaded with 1.25 k; positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified. Symbol osc(dig) Parameter Conditions Min Typ Max Unit TDA6650ATT/C3/S2; phase noise, carrier to sideband noise in digital TDA6651ATT/C3/S2; TDA6651ATT/C3/S3 application 1 kHz frequency offset; fcomp = 4 MHz; see Figure 8, 27 and 28 10 kHz frequency offset; worst case in the frequency range; see Figure 9, 27 and 28 100 kHz frequency offset; worst case in the frequency range; see Figure 10, 27 and 28 1.4 MHz frequency offset; worst case in the frequency range; see Figure 27 and 28 osc(hyb) phase noise, carrier to TDA6650ATT/C3; TDA6651ATT/C3 sideband noise in hybrid 1 kHz frequency offset; application fcomp = 4 MHz; see Figure 11, 29 and 30 10 kHz frequency offset; worst case in the frequency range; see Figure 12, 29 and 30 100 kHz frequency offset; worst case in the frequency range; see Figure 13, 29 and 30 1.4 MHz frequency offset; worst case in the frequency range; see Figure 29 and 30 RSCp-p ripple susceptibility of VCC (peak-to-peak value) oscillator operating frequency oscillator frequency fosc(V) fosc(T) oscillator frequency shift with supply voltage oscillator frequency drift with temperature T = 25 C; VCC = 5 V; with compensation
[7] [8]
85
90
-
dBc/Hz
87
94
-
dBc/Hz
104
112
-
dBc/Hz
-
116
-
dBc/Hz
80
86
-
dBc/Hz
85
92
-
dBc/Hz
104
115
-
dBc/Hz
-
115
-
dBc/Hz
VCC = 5 V 5 %; worst case in the frequency range; ripple frequency 500 kHz
[10]
15
140
-
mV
High band oscillator fosc 414 522 300 1100 824.143 MHz 824.143 MHz kHz kHz
[9]
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
26 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics ...continued VCCA = VCCD = 5 V; Tamb = 25 C; values are given for an asymmetrical IF output loaded with a 75 load or with a symmetrical IF output loaded with 1.25 k; positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified. Symbol osc(dig) Parameter Conditions Min Typ Max Unit TDA6650ATT/C3/S2; phase noise, carrier to sideband noise in digital TDA6651ATT/C3/S2; TDA6651ATT/C3/S3 application 1 kHz frequency offset; fcomp = 4 MHz; see Figure 8, 27 and 28 10 kHz frequency offset; worst case in the frequency range; see Figure 9, 27 and 28 100 kHz frequency offset; worst case in the frequency range; see Figure 11, 27 and 28 1.4 MHz frequency offset; worst case in the frequency range; see Figure 27 and 28 osc(hyb) phase noise, carrier to TDA6650ATT/C3; TDA6651ATT/C3 sideband noise in hybrid 1 kHz frequency offset; application fcomp = 4 MHz; see Figure 11, 29 and 30 10 kHz frequency offset; worst case in the frequency range; see Figure 12, 29 and 30 100 kHz frequency offset; worst case in the frequency range; see Figure 13, 29 and 30 1.4 MHz frequency offset; worst case in the frequency range; see Figure 29 and 30 RSCp-p ripple susceptibility of VCC (peak-to-peak value) output impedance VCC = 5 V 5 %; worst case in the frequency range; ripple frequency 500 kHz asymmetrical IF output RS at 57 MHz LS at 57 MHz symmetrical IF output RS at 57 MHz LS at 57 MHz Rejection at the IF output (IF amplifier in asymmetrical mode) INTdiv INTxtal divider interferences in IF level crystal oscillator interferences rejection worst case VIF = 100 dBV; worst case in the frequency range
[11] [10]
80
85
-
dBc/Hz
85
91
-
dBc/Hz
104
112
-
dBc/Hz
-
117
-
dBc/Hz
80
86
-
dBc/Hz
82
88
-
dBc/Hz
104
112
-
dBc/Hz
-
117
-
dBc/Hz
15
40
-
mV
IF amplifier Zo 50 4.7 100 10 20 -50 nH nH dBV dBc
[12]
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
27 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics ...continued VCCA = VCCD = 5 V; Tamb = 25 C; values are given for an asymmetrical IF output loaded with a 75 load or with a symmetrical IF output loaded with 1.25 k; positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified. Symbol INTf(step) Parameter step frequency rejection Conditions VIF = 100 dBV; worst case in the frequency range digital application TDA6650ATT/C3/S2, TDA6651ATT/C3/S2 digital application TDA6651ATT/C3/S3 hybrid application TDA6650ATT/C3, TDA6651ATT/C3 INTXTH crystal oscillator harmonics in the IF frequency bits AL[2:0] = 000
[14] [13]
Min
Typ
Max
Unit
-
-
-50
dBc
-
-
-35 -57 50
dBc dBc dBV
AGC output (IF amplifier in asymmetrical mode): pin AGC AGCTOP(p-p) AGC take-over point (peak-to-peak level) Isource(fast) Isource(slow) Vo source current fast source current slow output voltage maximum level TDA6650ATT/C3; TDA6651ATT/C3; TDA6650ATT/C3/S2; TDA6651ATT/C3/S2 TDA6651ATT/C3/S3 minimum level Vo(dis) output voltage with AGC bits AL[2:0] = 111 disabled TDA6650ATT/C3; TDA6651ATT/C3; TDA6650ATT/C3/S2; TDA6651ATT/C3/S2 TDA6651ATT/C3/S3 VRF(slip) RF voltage range to switch the AGC from active to not active mode low threshold AGC output voltage high threshold AGC output voltage leakage current AGC bit = 0 or AGC not active AGC bit = 1 or AGC active bits AL[2:0] = 110; 0 < VAGC < 3.5 V
[15]
122.5 7.5 185 3.45
124 9.0 220 3.55
125.5 11.6 280 3.8
dBV A nA V
3.3 0 3.45
3.55 3.55
3.8 0.1 3.8
V V V
3.3 -
3.55 -
3.8 0.5
V dB
VRML VRMH ILO
[1]
0 3.2 -50
3.55 -
2.8 3.8 +50
V V nA
Important recommendation: to obtain the performances mentioned in this specification, the serial resistance of the crystal used with this oscillator must never exceed 120 . The crystal oscillator is guaranteed to operate at any supply voltage between 4.5 V and 5.5 V and at any temperature between -20 C and Tamb(max), as defined in Section 10. The drive level is expected with a 50 series resistance of the crystal at series resonance. The drive level will be different with other series resistance values. The VXTOUT level is measured when the pin XTOUT is loaded with 5 k in parallel with 10 pF.
(c) NXP B.V. 2007. All rights reserved.
[2] [3]
TDA6650ATT_6651ATT_2
Product data sheet
Rev. 02 -- 2 February 2007
28 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
[4] [5] [6] [7] [8] [9]
The RF frequency range is defined by the oscillator frequency range and the Intermediate Frequency (IF). The 1 % cross modulation performance is measured with AGC detector turned off (AGC bits set to 110). The IF output signal stays stable within the range of the step frequency for any RF input level up to 120 dBV. Limits are related to the tank circuits used in Figure 27 and 28 for digital application or Figure 29 and 30 for hybrid application. Frequency bands may be adjusted by the choice of external components. The frequency shift is defined as a change in oscillator frequency when the supply voltage varies from VCC = 5 V to 4.5 V or from VCC = 5 V to 5.25 V. The oscillator is free running during this measurement. The frequency drift is defined as a change in oscillator frequency when the ambient temperature varies from Tamb = 25 C to 50 C or from Tamb = 25 C to 0 C. The oscillator is free running during this measurement.
[10] The supply ripple susceptibility is measured in the measurement circuit according to Figure 27 to Figure 30 using a spectrum analyzer connected to the IF output. An unmodulated RF signal is applied to the test board RF input. A sine wave signal with a frequency of 500 kHz is superimposed onto the supply voltage. The amplitude of this ripple signal is adjusted to bring the 500 kHz sidebands around the IF carrier to a level of -53.5 dB with respect to the carrier. [11] This is the level of divider interferences close to the IF frequency. The low and mid band inputs must be left open (i.e. not connected to any load or cable); the high band inputs are connected to an hybrid. [12] Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator. [13] The step frequency rejection is the level of step frequency sidebands related to the carrier. The measurement is done for VIF = 100 dBV. This specification point corresponds to the worst case observed in the frequency range. This parameter is specified for fstep = 142.86 kHz in digital applications and fstep = 62.5 kHz, 50 kHz or 142.86 kHz in hybrid application. [14] This is the level of the 13rd and 15th harmonics of the 4 MHz crystal oscillator into the IF output. [15] The AGC pin (pin 9 for TDA6650ATT and pin 30 for TDA6651ATT) must not be connected to a voltage higher than 3.6 V.
1 2 0.5
5 10
0.2
10 5
-j 10 5 2 1 0.5 0.2 40 MHz 200 MHz 0.2 0 +j
2 1
0.5
mce160
Fig 5. Input admittance (s11) of the low band mixer (40 MHz to 200 MHz); Yo = 20 mS
TDA6650ATT_6651ATT_2
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Product data sheet
Rev. 02 -- 2 February 2007
29 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
1 2 0.5
5 10
0.2
10 5
-j 10 5 2 1 0.5 0.2 100 MHz 0 +j
500 MHz
0.2
2 1
0.5
mce161
Fig 6. Input admittance (s11) of the mid band mixer (100 MHz to 500 MHz); Yo = 20 mS
1 0.5 2
800 MHz 0.2 350 MHz +j 0 -j 10 0.2 5 0.2 0.5 1 2 5 10 5 10
0.5 1
2
001aac088
Fig 7. Input impedance (s11) of the high band mixer (350 MHz to 800 MHz); Zo = 100
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
30 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
-80
001aac089
osc
(dBc/Hz)
-85
-90
-95
-100 150
250
350
450
550
650
750
fRF (MHz)
850
For measurement circuit see Figure 27 and Figure 28
Fig 8. 1 kHz phase noise typical performance in digital application
-85
001aac090
osc
(dBc/Hz)
-90
-95
-100
-105 150
250
350
450
550
650
750
fRF (MHz)
850
For measurement circuit see Figure 27 and Figure 28
Fig 9. 10 kHz phase noise typical performance in digital application
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
31 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
-105
001aac091
osc
(dBc/Hz)
-110
-115
-120 150
250
350
450
550
650
750
fRF (MHz)
850
For measurement circuit see Figure 27 and Figure 28
Fig 10. 100 kHz phase noise typical performance in digital application
-75
001aac092
osc
(dBc/Hz)
-80
-85
-90
-95
-100 150
250
350
450
550
650
750
fRF (MHz)
850
For measurement circuit see Figure 29 and Figure 30
Fig 11. 1 kHz phase noise typical performance in hybrid application
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
32 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
-85
001aac093
osc
(dBc/Hz)
-90
-95
-100 150
250
350
450
550
650
750
fRF (MHz)
850
For measurement circuit see Figure 29 and Figure 30
Fig 12. 10 kHz phase noise typical performance in hybrid application
-105
001aac094
osc
(dBc/Hz)
-110
-115
-120 150
250
350
450
550
650
750
fRF (MHz)
850
For measurement circuit see Figure 29 and Figure 30
Fig 13. 100 kHz phase noise typical performance in hybrid application
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
33 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
signal 50 source
LBIN or MBIN V 50
IFOUTA
27 spectrum analyzer Vo V'meas 50
e
Vmeas
DUT
Vi IFOUTB
RMS voltmeter
VCCA
fce747
Zi >> 50 Vi = 2 x Vmeas = 70 dBV. Vi = Vmeas + 6 dB = 70 dBV. Vo = V'meas + 3.75 dB.
Vo G v = 20 log ----- . Vi
ISDB-T and NTSC Japan. IF = 57 MHz.
Fig 14. Gain (GV) measurement in low and mid band with asymmetrical IF output
signal 50 source
LBIN or MBIN V 50
IFOUTA
transformer spectrum analyzer C N1 Vo N2 V'meas 50
e
Vmeas
DUT
Vi IFOUTB
RMS voltmeter
fce748
Zi >> 50 Vi = 2 x Vmeas = 70 dBV. Vi = Vmeas + 6 dB = 70 dBV. Vo = V'meas + 15 dB (transformer ratio N1/N2 = 5 and transformer loss).
Vo G v = 20 log ----- . Vi
ISDB-T and NTSC Japan. IF = 57 MHz. N1 = 10 turns. N2 = 2 turns. N1/N2 = 5.
Fig 15. Gain (GV) measurement in low and mid band with symmetrical IF output
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
34 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
NOISE SOURCE
BNC
RIM
LBIN or MBIN
27 IFOUTA
NOISE FIGURE METER
INPUT CIRCUIT
DUT
IFOUTB VCCA
fce750
NF = NFmeas - loss of input circuit (dB).
Fig 16. Noise figure (NF) measurement in low and mid band with asymmetrical IF output
BNC connector Cs
Cc
TL
to the IC mixer input
BNC connector
Ls
Cc
TL
to the IC mixer input
Lp
Cp
Lp
Cp
mce452
a. Schematic 1
For fRF = 150 MHz Loss = 0 dB. Cs = 0.8 pF to 8 pF trimmer. Cp = 0.4 pF to 2.5 pF trimmer. Lp = 4 turns, 4.5 mm, 0.4 mm wire air coil. Cc = 4.7 nF. TL: 50 semi rigid cable length = 75 mm.
b. Schematic 2
For fRF = 300 MHz Loss = 0.5 dB. Ls = 2 turns, 1.5 mm, 0.4 mm wire air coil. Cp = 8.2 pF in parallel with a 0.8 pF to 8 pF trimmer. Lp = 2 turns, 1.5 mm, 0.4 mm wire air coil. Cc = 4.7 nF. TL: 50 semi rigid cable length = 75 mm.
Fig 17. Input circuit for optimum noise figure measurement
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
35 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
FILTER
50
AM = 30 % 1 kHz A C unwanted signal source
eu
LBIN IFOUTA or MBIN
27
10 dB attenuator modulation analyzer
HYBRID
DUT
IFOUTB
50
Vo
57 MHz V Vmeas
50
50
B ew wanted signal source
D
VCCA
RMS voltmeter
001aac095
Vo = Vmeas + 3.75 dB. V'meas = Vo - (transformer ratio N1/N2 = 5 and loss). Wanted signal source at fRFpix is 80 dBV. Unwanted output signal at fsnd. The level of unwanted signal is measured by causing 0.3 % AM modulation in the wanted signal. N1 = 10 turns. N2 = 2 turns. N1/N2 = 5.
Fig 18. Cross modulation measurement in low and mid band with asymmetrical IF output
FILTER AM = 30 % 1 kHz 50 A eu unwanted signal source C LBIN or MBIN transformer IFOUTA 57 MHz 6 dB attenuator modulation analyzer C N1 Vo B ew wanted signal source D
50
HYBRID
DUT
IFOUTB
N2 V V'meas
50
50
RMS voltmeter
001aac096
V'meas = Vo - (transformer ratio N1/N2 = 5 and loss). Wanted signal source at fRFpix is 80 dBV. The level of unwanted signal Vo at fsnd is measured by causing 0.3 % AM modulation in the wanted output signal. N1 = 10 turns. N2 = 2 turns. N1/N2 = 5.
Fig 19. Cross modulation measurement in low and mid band with symmetrical IF output
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
36 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
signal 50 source A C HBIN1 IFOUTA
27 spectrum analyzer Vo V'meas 50
e
Vmeas
V
50
Vi
HYBRID
DUT
HBIN2 IFOUTB
B RMS 50 voltmeter
D
VCCA
fce751
Loss in hybrid = 1 dB. Vi = Vmeas - loss = 70 dBV. Vo = V'meas + 3.75 dB.
Vo G v = 20 log ----- . Vi
ISDB-T and NTSC Japan. IF = 57 MHz.
Fig 20. Gain (GV) measurement in high band with asymmetrical IF output
signal 50 source A C HBIN1 IFOUTA
transformer spectrum analyzer C N1 Vo N2 V'meas 50
e
Vmeas
V
50
Vi
HYBRID
DUT
B RMS 50 voltmeter
D
HBIN2
IFOUTB
fce752
Loss in hybrid = 1 dB. Vi = Vmeas - loss = 70 dBV. Vo = V'meas + 15 dB (transformer ratio N1/N2 = 5 and transformer loss).
Vo G v = 20 log ----- . Vi
ISDB-T and NTSC Japan. IF = 57 MHz.
Fig 21. Gain (GV) measurement in high band with symmetrical IF output
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
37 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
NOISE SOURCE
A
27 C HBIN1 IFOUTA
NOISE FIGURE METER
HYBRID B 50 D
DUT
HBIN2 IFOUTB
VCCA
fce753
Loss in hybrid = 1 dB. NF = NFmeas - loss.
Fig 22. Noise figure (NF) measurement in high band with asymmetrical IF output
FILTER AM = 30 % 1 kHz 50 A eu unwanted signal source C A C
27
10 dB attenuator modulation analyzer
HBIN1
IFOUTA 57 MHz V Vmeas
HYBRID
HYBRID
DUT
HBIN2 IFOUTB
Vo
50
50
B ew wanted signal source
D
50 50
B
D
VCCA
RMS voltmeter
001aac097
Vo = Vmeas + 3.75 dB. Wanted signal source at fRFpix is 70 dBV. Unwanted output signal at fsnd. The level of unwanted signal is measured by causing 0.3 % AM modulation in the wanted signal.
Fig 23. Cross modulation measurement in high band with asymmetrical IF output
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
38 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
AM = 30 % 1 kHz 50 eu unwanted signal source
transformer A C A C HBIN1 IFOUTA
6 dB attenuator
FILTER
modulation analyzer C N1 Vo N2 V V'meas 57 MHz
50
HYBRID
HYBRID
DUT
HBIN2 IFOUTB
50
B wanted signal source
D
50 50
B
D
ew
RMS voltmeter
001aac098
V'meas = Vo - (transformer ratio N1/N2 = 5 and loss). Wanted signal source at fRFpix is 70 dBV. The level of unwanted signal Vo at fsnd is measured by causing 0.3 % AM modulation in the wanted output signal. N1 = 10 turns. N2 = 2 turns. N1/N2 = 5.
Fig 24. Cross modulation measurement in high band with symmetrical IF output
signal 50 source
LBIN or MBIN V 50
IFOUTA
27 spectrum analyzer 50
e
Vmeas
DUT
IFOUTB
RMS voltmeter
VCCA
fce755
Zi >> 50 Vi = 2 x Vmeas. Vi = Vmeas + 6 dB.
Fig 25. Maximum RF input level without lock-out in low and mid band with asymmetrical IF output
signal 50 source A C HBIN1 IFOUTA
27 spectrum analyzer 50
e
Vmeas
V
50
Vi
HYBRID HBIN2
DUT
IFOUTB VCCA
B RMS voltmeter 50
D
fce756
Loss in hybrid = 1 dB. Vi = Vmeas - loss.
Fig 26. Maximum RF input level without lock-out in high band with asymmetrical IF output
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
39 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
The TDA6650ATT; TDA6651ATT PLL loop stability is guaranteed in the configuration of the Figure 27 to Figure 30. In this configuration, the external supply source is 30 V minimum, the pull-up resistor, R19 is 15 k and all of the local oscillators are aligned to operate at a maximum tuning voltage of 26 V. If the configuration is changed, there might be an impact on the loop stability. For any other configurations, a stability analysis must be performed. The conventional PLL AC model used for the stability analysis, is valid provided the external source (DC supply source or DC-to-DC converter) is able to deliver a minimum current that is equal to the charge pump current in use. The delivered current can be simply calculated with the following formula: V DC - V T I delivered = ------------------------ > I CP R pu where: Idelivered is the delivered current. VDC is the supply source voltage or DC-to-DC converter output voltage. VT is the tuning voltage. Rpu is the pull-up resistor between the DC supply source (or the DC-to-DC converter output) and the tuning line (R19 in Figure 27 to Figure 30). ICP is the charge pump current in use. (1)
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
40 of 54
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 02 -- 2 February 2007
(c) NXP B.V. 2007. All rights reserved. TDA6650ATT_6651ATT_2
NXP Semiconductors
J4 LOW
J3 MID
J1 HIGH1
J2 HIGH2
C7 1.5 pF N750 C6
L3 88 nH R07254 D1 BB182 C5 15 pF N750
R1 12
C4 4.7 nF
C3 4.7 nF
C1 4.7 nF
C2 4.7 nF
6 L4 TOKO 500 nH 1 C27 12 pF 2
4
1 pF N750
R2 5.6 k
* 4t
2 3 C26 12 pF HBIN1 HBIN2 MBIN LBIN RFGND IFFIL1 IFFIL2 BS4 AGC BS3 BS2 BS1 BVS ADC/BS5 SCL SDA AS XTOUT XTAL1
C34 1 (38) (1) 38 2 (37) (2) 37 (3) 36 3 (36) (4) 35 4 (35) (5) 34 5 (34) (6) 33 6 (33) 7 (32) TDA6650ATT (7) 32 8 (31) (TDA6651ATT) (8) 31 (9) 30 9 (30) (10) 29 10 (29) 11 (28) (11) 28 (12) 27 12 (27) (13) 26 13 (26) (14) 25 14 (25) (15) 24 15 (24) (16) 23 16 (23) (17) 22 17 (22) (18) 21 18 (21) (19) 20 19 (20) C19 18 pF Y1 4 MHz LOSCIN LOSCOUT OSCGND MOSCIN2 MOSCIN1 HOSCIN2 HOSCOUT2 HOSCOUT1 HOSCIN1 IFGND IFOUTA IFOUTB VCCA PLLGND VCCD CP VT n.c. XTAL2 VCC C15 4.7 nF C16 4.7 nF R13 6.8 k
30 V
R3 5.6 k D2 BB178 R4 5.6 k
L1 25 nH
33 pF N750 C33 33 pF N750
C11 1 pF N750 C12 1 pF N750 C13 1 pF VCC N750 C14 1 pF N750
TP1
AGC C28 150 nF D4 R20 1 k D5 R21 1 k D6 R22 1 k D7 R23 1 k D8 5 V bus R24 1 k VCC R14 ST1 1 k J8 123456 SCL R27 3.3 k R28 3.3 k SDA AS ST2 ADC R9 330 R10 330
D3 BB179 L2 16 nH R02255 C18 R6 27 R5 5.6 k 8.2 pF N470 R8 5.6 k C17 3.9 nF
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
VCC C21 47 nF C20 470 pF C23 4.7 nF R7 1 k
R11 330
5 V bus VCC
C29 4.7 nF
C31 10 F C32 10 F C30 10 F 1234 J5
R19 15 k J6
R26 27
J7 5 V bus
test
30 V
IF out
001aac099
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 27. Measurement circuit for digital application, with asymmetrical IF output and ISDB-T compliant loop filter
41 of 54
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 02 -- 2 February 2007
(c) NXP B.V. 2007. All rights reserved. TDA6650ATT_6651ATT_2
NXP Semiconductors
J4 LOW
J3 MID
J1 HIGH1
J2 HIGH2
C7 1.5 pF N750 C6
L3 88 nH R07254 D1 BB182 C5 15 pF N750
R1 12
C4 4.7 nF
C3 4.7 nF
C1 4.7 nF
C2 4.7 nF
6 L4 TOKO 500 nH 1 C27 12 pF 2 * 4t
4
1 pF N750
R2 5.6 k
C34
HBIN1 HBIN2 MBIN LBIN RFGND IFFIL1 IFFIL2 BS4 AGC BS3 BS2 BS1 BVS ADC/BS5 SCL SDA AS XTOUT XTAL1
R3 5.6 k D2 BB178 R4 5.6 k
2
3 C26 12 pF
TP1
AGC C28 150 nF D4 R20 1 k D5 R21 1 k D6 R22 1 k D7 R23 1 k D8 5 V bus R24 1 k VCC R14 ST1 1 k J8 123456 SCL R27 3.3 k R28 3.3 k SDA AS ST2 ADC R9 330 R10 330
1 (38) 2 (37) 3 (36) 4 (35) 5 (34) 6 (33) 7 (32) 8 (31) TDA6651ATT 9 (30) 10 (29) 11 (28) 12 (27) 13 (26) 14 (25) 15 (24) 16 (23) 17 (22) 18 (21) 19 (20) C19 18 pF
(1) 38 (2) 37 (3) 36 (4) 35 (5) 34 (6) 33 (7) 32 (8) 31 (9) 30 (10) 29 (11) 28 (12) 27 (13) 26 (14) 25 (15) 24 (16) 23 (17) 22 (18) 21 (19) 20
LOSCIN LOSCOUT OSCGND MOSCIN2 MOSCIN1 HOSCIN2 HOSCOUT2 HOSCOUT1 HOSCIN1 IFGND IFOUTA IFOUTB VCCA PLLGND VCCD CP VT n.c. XTAL2 VCC VCC
L1 25 nH
33 pF N750 C33 33 pF N750
C11 1 pF N750 C12 1 pF N750 C13 1 pF N750 C14 1 pF N750
D3 BB179 L2 16 nH R02255 C18 R6 27 R5 5.6 k 8.2 pF N470 R8 5.6 k C17 3.9 nF
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Y1 4 MHz
R11 330
C21 47 nF C16 4.7 nF R13 6.8 k
C24 4.7 nF
C23 4.7 nF C25 12 pF
R7 1 k
C15 4.7 nF
5 V bus VCC 30 V
C20 470 pF
C29 4.7 nF
C31 10 F C32 10 F C30 10 F 1234 J5
R19 15 k 30 V
1
2
3 TR1 TOKO 7451
6 J6
4
J7 5 V bus
test
IF out
001aac100
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 28. Measurement circuit for digital application, with symmetrical IF output and ISDB-T compliant loop filter
42 of 54
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 02 -- 2 February 2007
(c) NXP B.V. 2007. All rights reserved. TDA6650ATT_6651ATT_2
NXP Semiconductors
J4 LOW
J3 MID
J1 HIGH1
J2 HIGH2
C7 1.5 pF N750 C6
L3 88 nH R07254 D1 BB182 C5 15 pF N750
R1 12
C4 4.7 nF
C3 4.7 nF
C1 4.7 nF
C2 4.7 nF
6 L4 TOKO 500 nH 1 C27 12 pF 2
4
1 pF N750
R2 5.6 k
* 4t
2 3 C26 12 pF HBIN1 HBIN2 MBIN LBIN RFGND IFFIL1 IFFIL2 BS4 AGC BS3 BS2 BS1 BVS ADC/BS5 SCL SDA AS XTOUT XTAL1
C34 1 (38) (1) 38 2 (37) (2) 37 (3) 36 3 (36) (4) 35 4 (35) (5) 34 5 (34) (6) 33 6 (33) 7 (32) TDA6650ATT (7) 32 8 (31) (TDA6651ATT) (8) 31 (9) 30 9 (30) (10) 29 10 (29) 11 (28) (11) 28 (12) 27 12 (27) (13) 26 13 (26) (14) 25 14 (25) (15) 24 15 (24) (16) 23 16 (23) (17) 22 17 (22) (18) 21 18 (21) (19) 20 19 (20) C19 18 pF Y1 4 MHz LOSCIN LOSCOUT OSCGND MOSCIN2 MOSCIN1 HOSCIN2 HOSCOUT2 HOSCOUT1 HOSCIN1 IFGND IFOUTA IFOUTB VCCA PLLGND VCCD CP VT n.c. XTAL2 VCC C15 4.7 nF C16 4.7 nF R13 1.8 k
30 V
R3 5.6 k D2 BB178 R4 5.6 k
L1 25 nH
33 pF N750 C33 33 pF N750
C11 1 pF N750 C12 1 pF N750 C13 1 pF VCC N750 C14 1 pF N750
TP1
AGC C28 150 nF D4 R20 1 k D5 R21 1 k D6 R22 1 k D7 R23 1 k D8 5 V bus R24 1 k VCC R14 ST1 1 k J8 123456 SCL R27 3.3 k R28 3.3 k SDA AS ST2 ADC R9 330 R10 330
D3 BB179 L2 16 nH R02255 C18 R6 27 R5 5.6 k 8.2 pF N470 R8 5.6 k C17 4.7 nF
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
VCC C21 100 nF C20 2.7 nF C23 4.7 nF R7 1 k
R11 330
5 V bus VCC
C29 4.7 nF
C31 10 F C32 10 F C30 10 F 1234 J5
R19 15 k J6
R26 27
J7 5 V bus
test
30 V
IF out
001aac044
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 29. Measurement circuit for hybrid application, with asymmetrical IF output and loop filter for NTSC Japan and ISDB-T standards
43 of 54
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 02 -- 2 February 2007
(c) NXP B.V. 2007. All rights reserved. TDA6650ATT_6651ATT_2
NXP Semiconductors
J4 LOW
J3 MID
J1 HIGH1
J2 HIGH2
C7 1.5 pF N750 C6
L3 88 nH R07254 D1 BB182 C5 15 pF N750
R1 12
C4 4.7 nF
C3 4.7 nF
C1 4.7 nF
C2 4.7 nF
6 L4 TOKO 500 nH 1 C27 12 pF 2 * 4t
4
1 pF N750
R2 5.6 k
C34
HBIN1 HBIN2 MBIN LBIN RFGND IFFIL1 IFFIL2 BS4 AGC BS3 BS2 BS1 BVS ADC/BS5 SCL SDA AS XTOUT XTAL1
R3 5.6 k D2 BB178 R4 5.6 k
2
3 C26 12 pF
TP1
AGC C28 150 nF D4 R20 1 k D5 R21 1 k D6 R22 1 k D7 R23 1 k D8 5 V bus R24 1 k VCC R14 ST1 1 k J8 123456 SCL R27 3.3 k R28 3.3 k SDA AS ST2 ADC R9 330 R10 330
1 (38) 2 (37) 3 (36) 4 (35) 5 (34) 6 (33) 7 (32) 8 (31) TDA6651ATT 9 (30) 10 (29) 11 (28) 12 (27) 13 (26) 14 (25) 15 (24) 16 (23) 17 (22) 18 (21) 19 (20) C19 18 pF
(1) 38 (2) 37 (3) 36 (4) 35 (5) 34 (6) 33 (7) 32 (8) 31 (9) 30 (10) 29 (11) 28 (12) 27 (13) 26 (14) 25 (15) 24 (16) 23 (17) 22 (18) 21 (19) 20
LOSCIN LOSCOUT OSCGND MOSCIN2 MOSCIN1 HOSCIN2 HOSCOUT2 HOSCOUT1 HOSCIN1 IFGND IFOUTA IFOUTB VCCA PLLGND VCCD CP VT n.c. XTAL2 VCC VCC
L1 25 nH
33 pF N750 C33 33 pF N750
C11 1 pF N750 C12 1 pF N750 C13 1 pF N750 C14 1 pF N750
D3 BB179 L2 16 nH R02255 C18 R6 27 R5 5.6 k 8.2 pF N470 R8 5.6 k C17 4.7 nF
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
R11 330
Y1 4 MHz
C21 100 nF C16 4.7 nF R13 1.8 k
C24 4.7 nF
C23 4.7 nF C25 12 pF
R7 1 k
C15 4.7 nF
5 V bus VCC 30 V
C20 2.7 nF
C29 4.7 nF
C31 10 F C32 10 F C30 10 F 1234 J5
R19 15 k 30 V
1
2
3 TR1 TOKO 7451
6 J6
4
J7 5 V bus
test
IF out
001aac101
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 30. Measurement circuit for hybrid application, with symmetrical IF output and loop filter for NTSC Japan and ISDB-T standards
44 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
13. Application information
13.1 Tuning amplifier
The tuning amplifier is capable of driving the varicap voltage without an external transistor. The tuning voltage output must be connected to an external load of 15 k which is connected to the tuning voltage supply rail. The loop filter design depends on the oscillator characteristics and the selected reference frequency as well as the required PLL loop bandwidth. Applications with the TDA6650ATT; TDA6651ATT have a large loop bandwidth, in the order of a few tens of kHz. The calculation of the loop filter elements has to be done for each application, it depends on the reference frequency and charge pump current.
13.2 Crystal oscillator
The TDA6650ATT; TDA6651ATT needs to be used with a 4 MHz crystal in series with a capacitor with a typical value of 18 pF, connected between pin XTAL1 and pin XTAL2. Philips crystal 4322 143 04093 is recommended. When choosing a crystal, take care to select a crystal able to withstand the drive level of the TDA6650ATT; TDA6651ATT without suffering from accelerated ageing. For optimum performances, it is highly recommended to connect the 4 MHz crystal without any serial resistance. The crystal oscillator of the TDA6650ATT; TDA6651ATT should not be driven (forced) from an external signal. Do not use the signal on pins XTAL1 or XTAL2, or the signal present on the crystal, to drive an external IC or for any other use as this may dramatically degrade the phase noise performance of the TDA6650ATT; TDA6651ATT.
13.3 Examples of I2C-bus program sequences
Table 21 to Table 26 show various sequences where: S = START A = acknowledge P = STOP. The following conditions apply: LO frequency is 800 MHz fcomp = 142.86 kHz N = 5600 BS3 output port is on and all other ports are off: thus the high band is selected Charge pump current ICP = 600 A Normal mode, with XTOUT buffer on IAGC = 220 nA AGC take-over point is set to 112 dBV (p-p) Address selection is adjusted to make address C2 valid. To fully program the device, either sequence of Table 21 or Table 22 can be used, while other arrangements of the bytes are also possible.
TDA6650ATT_6651ATT_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
45 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Complete sequence 1 Divider byte 1 15 A Divider byte 2 E0 A Control byte 1[1] C9 A Control byte 2 E4 A Control byte 1[2] 84 A Stop P
Table 21. Start S
[1] [2]
Address byte C2 A
Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1 and AL0.
Table 22. Start S
[1] [2]
Complete sequence 2 Control byte 1[1] C9 A Control byte 2 E4 A Divider byte 1 15 A Divider byte 2 E0 A Control byte 1[2] 84 A Stop P
Address byte C2 A
Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1 and AL0.
Table 23. Start S Table 24. Start S
[1]
Sequence to program only the main divider ratio Address byte C2 A Divider byte 1 15 A Divider byte 2 E0 A Stop P
Sequence to change the charge pump current, the ports and the test mode. If the reference divider ratio is changed, it is necessary to send the DB1 and DB2 bytes Address byte C2 A Control byte 1[1] C9 A Control byte 2 E4 A Stop P
Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
Table 25. Start S
[1]
Sequence to change the test mode. If the reference divider ratio is changed, it is necessary to send the DB1 and DB2 bytes Address byte C2 A Control byte 1[1] C9 A Stop P
Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
Table 26. Start S
[1]
Sequence to change the charge pump current, the ports and the AGC data Address byte C2 A Control byte 1[1] 82 A Control byte 2 E4 A Stop P
Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1 and AL0.
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
46 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Sequence to change only the AGC data Address byte C2 A Control byte 1[1] 84 A Stop P
Table 27. Start S
[1]
Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1 and AL0.
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
47 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
14. Package outline
TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0.5 mm
SOT510-1
D
E
A X
c y HE vMA
Z
38
20
A2 pin 1 index A1
(A 3)
A
Lp L
1
e bp
19
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.5 HE 6.4 L 1 Lp 0.7 0.5 v 0.2 w 0.08 y 0.08 Z (1) 0.49 0.21
8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT510-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-02-18 05-11-02
Fig 31. Package outline SOT510-1 (TSSOP38)
TDA6650ATT_6651ATT_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
48 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits.
16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
TDA6650ATT_6651ATT_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
49 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 28 and 29
Table 28. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 29. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32.
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
50 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Abbreviations
Table 30. Acronym ADC AGC ISDB-T NTSC PLL PMOS QAM VCO VCR Abbreviations Description Analog-to-Digital Converter Automatic Gain Control Integrated Services Digital Broadcasting - Terrestrial National Telecommunications Standards Committee Phase-Locked Loop Positive Channel Metal Oxide Semiconductor Quadrature Amplitude Modulation Voltage-Controlled Oscillator Video Cassette Recorder
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
51 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
18. Revision history
Table 31. Revision history Release date 20070202 Data sheet status Product data sheet Change notice Supersedes TDA6650ATT_6651ATT_1 Document ID TDA6650ATT_6651ATT_2 Modifications:
* * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Created Table 1 and updated Table 3 and 20 with new type numbers, emphasizing the different types for hybrid and digital only applications. Two values changed in Table 20; page 27 VAGC < VCC replaced with VAGC < 3.5 V and for Vo(dis) new minimum value of 3.3 V added. Product data sheet -
TDA6650ATT_6651ATT_1 (9397 750 14179)
20041214
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
52 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
19.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
20. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
TDA6650ATT_6651ATT_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 February 2007
53 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
21. Contents
1 2 3 3.1 4 5 6 6.1 6.2 7 7.1 7.2 7.3 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.3 9 10 11 12 13 13.1 13.2 13.3 14 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 19.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Application summary . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Mixer, Oscillator and PLL (MOPLL) functions. . 6 I2C-bus voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7 Phase noise, I2C-bus traffic and crosstalk . . . . 7 2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . 8 I Write mode; R/W = 0 . . . . . . . . . . . . . . . . . . . . 8 I2C-bus address selection. . . . . . . . . . . . . . . . 10 XTOUT output buffer and mode setting . . . . . 10 Step frequency setting . . . . . . . . . . . . . . . . . . 10 AGC detector setting . . . . . . . . . . . . . . . . . . . 11 Charge pump current setting . . . . . . . . . . . . . 11 Read mode; R/W = 1 . . . . . . . . . . . . . . . . . . . 12 Status at power-on reset. . . . . . . . . . . . . . . . . 13 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 14 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal characteristics. . . . . . . . . . . . . . . . . . 19 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application information. . . . . . . . . . . . . . . . . . 45 Tuning amplifier. . . . . . . . . . . . . . . . . . . . . . . . 45 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 45 Examples of I2C-bus program sequences . . . 45 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48 Handling information. . . . . . . . . . . . . . . . . . . . 49 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Introduction to soldering . . . . . . . . . . . . . . . . . 49 Wave and reflow soldering . . . . . . . . . . . . . . . 49 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 49 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 50 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 52 Legal information. . . . . . . . . . . . . . . . . . . . . . . 53 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 53 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 20 21 Contact information . . . . . . . . . . . . . . . . . . . . 53 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 February 2007 Document identifier: TDA6650ATT_6651ATT_2

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